[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Jun 28 07:14:55 BST 2019


http://bugs.libre-riscv.org/show_bug.cgi?id=44

--- Comment #36 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok that's basically it: the infrastructure's in place.  it should
be clear that:

* FPDivStage0Mod is the first class that converts incoming
  (normalised) data into Q+R (whatever: the stuff that
  eventually becomes the div and rem)
* FPDivStage1Mod is part of the huuuuge chain that will
  take Q+R (whatever) and output Q+R (whatever)
* FPDivStage2Mod is the *last* one that takes Q+R (whatever)
  as input and drops it into the mantissa.

given that div *may* need the mantissa normalising to within a
range 0.5 to 1.0 (or somesuch), we *may* need an *extra*
pre-normalising stage.

it should be pretty clear from divstages.py how that can be
added.


index 94c8a78..e1f8b11 100644 (file)
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -16,6 +16,7 @@ from ieee754.fpcommon.postcalc import FPAddStage1Data
 # TODO: write these
 from .div0 import FPDivStage0Mod
 from .div1 import FPDivStage1Mod
+from .div2 import FPDivStage2Mod


 class FPDivStages(FPState, SimpleHandshake):
@@ -40,10 +41,12 @@ class FPDivStages(FPState, SimpleHandshake):
         # TODO.  clearly, this would be a for-loop, here, creating
         # a huge number of stages (if radix-2 is used).  interestingly
         # the number of stages will be data-dependent.
-        m0mod = FPDivStage0Mod(self.width, self.id_wid)
-        m1mod = FPDivStage1Mod(self.width, self.id_wid)
+        divstages = [FPDivStage0Mod(self.width, self.id_wid)]
+        for i in range(self.width): # XXX TODO: work out actual number needed
+            divstages.append(FPDivStage1Mod(self.width, self.id_wid))
+        divstages.append(FPDivStage2Mod(self.width, self.id_wid))

-        chain = StageChain([m0mod, m1mod])
+        chain = StageChain(divstages)
         chain.setup(m, i)

         self.o = m1mod.o

-- 
You are receiving this mail because:
You are on the CC list for the bug.


More information about the libre-riscv-dev mailing list