[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=99

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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             Blocks|                            |48
    NLnet milestone|---                         |NLnet.2019.02

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://github.com/wmy367/Radix-2-division/blob/master/Radix_2_div.v

example radix 2 divide which could probably be pipelined.


Referenced Bugs:

http://bugs.libre-riscv.org/show_bug.cgi?id=48
[Bug 48] Complete IEEE754 floating point pipeline
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