[libre-riscv-dev] Introducing Myself
hacks2019 at platen-software.de
Sat Jun 8 06:19:50 BST 2019
On 06/08/2019 12:15 AM, Luke Kenneth Casson Leighton wrote:
> On Fri, Jun 7, 2019 at 5:16 PM Tobias Platen
> <hacks2019 at platen-software.de> wrote:
>>>> My Bachelor thesis was about implementing a cache for that processor.
>>> that's interesting, because one of the next tasks coming up quite soon
>>> will be to do that. would you be interested to tackle that? yes
>>> there is NLnet donations available.
>> Definitively I am interested in doing that. Where do I begin with?
> great! you'll need this repo:
> first though please do bear in mind, we have a charter. it's explained here:
I know about the charter and I find its mostly ok.
> do let us know if it's ok?
> devnotes are here, they're quite straightforward:
> dependencies: yosys (from latest git), nmigen (from latest git), and a
> minimum of python 3.6. nosetests3 is also nice to have, and at some
> point epydoc will go into the Makefile(s).
I first will have to install the now python version. Since I have
Trisquel 8 on my laptop, I currently have only Python 3.5.
> the TLB and cache codebase is here:
> the VM milestone is here:
> it needs breaking down into sub-tasks (NLnet pays on milestone 100%
> completion), one of those being the L1 and L2 caches.
> i've been slowly morphing ariane source code over to nmigen. am
> currently working through miss_handler.py
> that's quite a lot already :)
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