[libre-riscv-dev] Introducing Myself

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jun 7 23:15:08 BST 2019

On Fri, Jun 7, 2019 at 5:16 PM Tobias Platen
<hacks2019 at platen-software.de> wrote:

> >> My Bachelor thesis was about implementing a cache for that processor.
> > that's interesting, because one of the next tasks coming up quite soon
> > will be to do that.  would you be interested to tackle that?  yes
> > there is NLnet donations available.
> Definitively I am interested in doing that. Where do I begin with?

great!  you'll need this repo:

first though please do bear in mind, we have a charter.  it's explained here:

do let us know if it's ok?

devnotes are here, they're quite straightforward:

dependencies: yosys (from latest git), nmigen (from latest git), and a
minimum of python 3.6.  nosetests3 is also nice to have, and at some
point epydoc will go into the Makefile(s).

the TLB and cache codebase is here:

the VM milestone is here:

it needs breaking down into sub-tasks (NLnet pays on milestone 100%
completion), one of those being the L1 and L2 caches.

i've been slowly morphing ariane source code over to nmigen.  am
currently working through miss_handler.py

that's quite a lot already :)


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