[libre-riscv-dev] SV VLIW format

[Luke Kenneth Casson Leighton]

Added an 8 bit RegSpec and PredicateSpec format that is based on SVPrefix,
means that a lot more registers can be vectorised and predicated in a lot
less space.

Tempted to increase the number of instruction bits so that the calculation
is e.g. 112 plus 16 times 0bNNN

That would give 32 more bits to play with.

Also the actual implementation has to be thought through? What about the
PC? Can you branch or call a function? What about traps?

L.



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