[libre-riscv-dev] uniform instruction format

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Jun 15 16:50:45 BST 2019


deviates too far from RV32, it's unrecogniseable, and would require a
custom decoder that has nothing in common with an RV32 decoder.

the very very quickly written (1-2 days) format i was expecting is to
embed the 32 bit standard format(s) into a 64 bit (or greater) field,
and to have extra bits tacked on in fixed locations for VL, 1 bit fof
"rs1 is vector or rs1 is scalar", "rs2 is vector or rs2 is scalar" and
so on.

given that hard-coded wire positions are simply routing with no logic
required, the actual bit positions do not matter in the slightest.

also we do not need additional immediate bits, as there is no way that
these can be represented in the original RV32 opcodes.

given that this is an *internal* representation that will never make
it out into an actual assembler, adding extra immediate bits just
results in extra decode logic that will never be used.


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