[libre-riscv-dev] LD/ST address matcher
programmerjake at gmail.com
Tue Jun 4 05:31:53 BST 2019
On Mon, Jun 3, 2019, 19:29 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Tuesday, June 4, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > .
> >> >
> >> assuming 4-input gates can be used for and-reduction, I had calculated
> >> count above to be 1904 inverter equivalents for the 8x8 16-bit
> >> grid (3808 transistors)
> > That's tolerable. Missed it.
> > Would still feel more comfortable with a hybrid approach, as the hash
> > alone will definitely miss certain entries that a straight addr[4..11]
> > would definitely detect.
> > Mitch picked 4..11 as you can see from his earlier reply because it
> > corresponds with cache lines.
> Jacob what do you think, is there a hash algorithm out there that works on
> say 9 or even 16 bits, reducing them down to say 4 or 5?
Yes, CRCs. Most other hash functions will also work if the 9 or 16 bits are
> And did you see that Mitch confirms that the AGEN detection needs to be on
> the PHYS addr as well ad the Virt one?
> So it is no longer 64 bits to hash it is well over 100.
If the physical address makes it into the hash, the virtual address must be
ignored, so 40-50 bits. If the virtual address is not ignored, you can
accidentally think that two different virtual address don't map to the same
physical memory location when they actually do.
If the physical address is not in the hash, you have to fall back to only
comparing the bits that can't be mapped to the same physical address, the
least significant 12 bits. If you check additional more significant virtual
address bits, you can accidentally think that two different virtual address
don't map to the same physical memory location when they actually do.
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