[libre-riscv-dev] LD/ST address matcher

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jun 4 03:29:07 BST 2019

On Tuesday, June 4, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> .
>> >
>> assuming 4-input gates can be used for and-reduction, I had calculated the
>> count above to be 1904 inverter equivalents for the 8x8 16-bit comparator
>> grid (3808 transistors)
> That's tolerable. Missed it.
> Would still feel more comfortable with a hybrid approach, as the hash
> alone will definitely miss certain entries that a straight addr[4..11]
> would definitely detect.
> Mitch picked 4..11 as you can see from his earlier reply because it
> corresponds with cache lines.
Jacob what do you think, is there a hash algorithm out there that works on
say 9 or even 16 bits, reducing them down to say 4 or 5?

And did you see that Mitch confirms that the AGEN detection needs to be on
the PHYS addr as well ad the Virt one?

So it is no longer 64 bits to hash it is well over 100.


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