[libre-riscv-dev] LD/ST address matcher

whygee at f-cpu.org whygee at f-cpu.org
Tue Jun 4 01:13:02 BST 2019

On 2019-06-04 01:59, Jacob Lifshay wrote:
> I think the hash technique would be less expensive than your estimate:
> an and gate is 6 transistors (4 for nand then 2 for inverter)
> an xor gate can be 6 transistors: http://tinyurl.com/yyygzebc

There are many configurations for XOR in CMOS :-)
I have listed several there :

More information about the libre-riscv-dev mailing list