[libre-riscv-dev] [Bug 102] New: IEEE754 pipeline "early out" needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=102

            Bug ID: 102
           Summary: IEEE754 pipeline "early out" needed
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: ALU (including IEEE754 16/32/64-bit FPU)
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

special-cases do not need to go through the pipeline.  however this means
that two results can be generated in one clock.  fortunately, the muxid
protects two results from occurring with the same muxid (Fan-in, Fan-out
ReservationStation class).

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