[libre-riscv-dev] [Bug 92] New: Implement in order instruction retire refcounting

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=92

            Bug ID: 92
           Summary: Implement in order instruction retire refcounting
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

Shadows need to be cast across instructions, to preserve instruction order,
however it is quite detailed and needs two refcounts, one for registers to
protect inorder writes to the regfile, and another for the MemRefs. Also if
using CSR Dependency Management, one may be needed there, too.

Detailed writeup here

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-June/001660.html

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