[libre-riscv-dev] [Bug 92] Implement in order instruction retire refcounting

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Thu Jun 6 06:46:27 BST 2019


--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
The proposed idea has a problem: the counter compares are effectively CAM
compares. Multiple AND gates to check that the high bits are nonzero.

This for every single FU, it is just too expensive.

An alternative idea is to preallocate, at instruction issue time, the register
write port to which the instruction will commit its result.

This by having a separate set of shadows for the write ports.

This unfortunately has the side effect of reducing parallelism as the
instructions may complete well before each other, and, if allowed to commit via
another port, clearly would allow forward progress that was otherwise missed.

Hopefully operand forwarding will mitigate this somewhat.

There must be better alternatives.

Perhaps even whilst the allocations are not to ports per se, they may be at
least identification of "candidates for selection to commit to any port".

Or, perhaps, it is not a problem after all. Instruction order is to be
preserved. If one shadow bank is not ready, allowing another to commit would
mean getting out of order.

Needs more thought.

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