[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=99

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
radix-8 3-2 CSA:

figure 3.21 from p42:

def csa(input, mux):
  x, c = halfadd(input[0], input[1])
  x1, c1 = halfadd(c, mux)
  return [x & x1, c]

def csa32(input, mux): # 2 bit input, 2 bit mux)
  x = csa(input, mux[0])
  return csa(x, mux[1])

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