[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=99

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
figure 3.18 p40 ep08_15
TODO: edit/sort this, can't work out mux31 from figure 3.13, p34

# input = [a, b, c], sel = [10, 00, 01] to represent {-d, 0, +d}
def mux31(input, sel):
   if sel == 10:
       return a

def mux51(input, sel): # input = [a,b,c,d,e]
   x = mux31(input[:3], sel[0])
   return mux31([x] + input[3:], sel[1])

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