[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Jun 28 21:20:27 BST 2019


--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Just realised that FPDIVStages is a single combinatorial stage, can't do that.

Tomorrow I will do pipeline.py pipe1,2,3 as pipesc, pipe1,2,3,4, pipepost

The first one pipe1 will need a tiny bit of conversion at the front.

The last one, pipe4, again conversion at the end.

All of pipe1 to 6 will need to be radix8 (three bits at a time) and 2
StageChained radix8 to give 6 bits at a time.

That gives only 4 stages, and we stand a chance of the pipeline not being
insanely long.

6 stages is still one hell of a lot because it will need 6 FUs at the Matrix to
keep 100% throughput.

With 128 registers and likely something around 30 FUs we could be looking at a
quarter million gates just for the Dependency Matrices.

Getting that number down is really critical.

So the less stages in FPDIV FP32 the bettet.

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