[libre-riscv-dev] uniform instruction format

[Luke Kenneth Casson Leighton]

https://libre-riscv.org/simple_v_extension/sv_prefix_proposal/

from an idea on isa-dev, about LD/ST-MULTI, and from a format from the VLIW
that allows VL/MVL to be set (and the value put into a reg), i realised
that it's also possible to use the same VL/MVL-setting trick in the 64-bit
format... *and* there is room for an extra set of bits to take
rd/rs1/rs2/rs3 up to the full 128 register range.

* the 48-bit prefix allows setting of scalar/vector
* the 48-bit prefix provides one extra bit of register range for
rd/rs1/rs2/rs3.
* the 48-bit prefix allows setting of predicates (single and twin mode)
* the 48-bit prefix does not provide setting of VL/MVL.
* the 48-bit prefix only allows vectors to start on even-numbered register
boundaries
* the 64-bit extra-prefix allows the full 128 reg range
* the 64-bit extra-prefix allows setting of VL and MVL.

that gives a way to do LD/ST-MULTI in a single 64-bit instruction!  cool!

thoughts?

l.