[libre-riscv-dev] store computation unit

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jun 4 05:37:20 BST 2019

On Tuesday, June 4, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> Thx Mitch, going to have to absorb and think this one through.
> ---------- Forwarded message ----------
> From: *Mitchalsup* <mitchalsup at aol.com>
> Date: Tuesday, June 4, 2019
> Subject: Re: store computation unit
> To: lkcl at lkcl.net
> Mitch Alsup
> MitchAlsup at aol.com
> -----Original Message-----
> From: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> To: Mitchalsup <mitchalsup at aol.com>; Libre-RISCV General Development <
> libre-riscv-dev at lists.libre-riscv.org>
> Sent: Mon, Jun 3, 2019 5:41 pm
> Subject: Re: store computation unit
> On Mon, Jun 3, 2019 at 7:51 PM Mitchalsup <mitchalsup at aol.com> wrote:
> > > Got it.  This is remarkably similar to the problem I ran into
> > > on the FU-FU Matrix, where ADD r1 r1 r1 would cause
> > > the FUFU Matrix to create both a spurious RaW *and* WaR hazard...
> > > on itself.
> >
> > This is where my writeup has a flaw:: Write dependencies need to be
> flopped and not driven continuously.
> err, err... if you mean that the incoming ST signal is only ASSERTed
> for one clock cycle (when Issue is also raised), that has me
> concerned.
> No, what I mean is closer to the contrapositive of what you wrote::
> a) you accumulate the pending write dependencies and store them in a
> vector of flops
> one bit per dependence; the whole vector associated with the FU.
> b) as dependencies relax you clear one flop
> c) as dependent ops are performed, you clear that flop
> d) when the flop contains no set bits, this instruction is no longer being held
> up by dependencies.

So this is the mirror equivalent of the FU Regs Matrix, except for memory
not Registers.

I am guessing, from the mirror functionality of FU Regs:

Its horizontal vectors are ORed to produce the ST Pending that then goes
into the Memory DM.

It would make sense for a LD Pending to also be generated, however I think
that is heading in the direction of TSO (Total Store Order) and RaR.

Not sure.


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