[libre-riscv-dev] store computation unit

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Jun 9 13:48:39 BST 2019

I spent the afternoon merging (overlaying) the partial address matcher
matrix with a FURegs Matrix, adapted to be NxN instead of NxM. This is
named the MDM (Memory Dependency Matrix)

LOADs are treated as if they were register writes, and STOREs as if they
were register reads.

All instructions going into the Matrix (whether LD or ST) are made to
depend on all prior instructions, with the new "register" (a RD or WR aka
ST or LD) going into the Matrix too.  Atomic operations would raise both LD
and ST.

At the time of issue we have no idea if there is a possible address clash.
Bear in mind if a clash cannot be determined, the default action is to
treat the instructions as dependent, and to be actioned in-order.

There is a *separate* FURegs Matrix that takes the address and src/dest
reg#s from the LD/ST operation.  These are passed to an AGEN Computation
Unit that takes a cycle or so to calculate the address. On doing so it
raises a "Request Addr" flag.

>From all AGEN CUs, the array of REQADDR flags, along with the array of
addresses, go into the Address Matcher, which is now overlaid on top of the
Memory Dependency Matrix.

With some addresses now known, the Matcher produces a 2D array of matches.
This being 2D because the design is targetting multi issue (single issue
could so the AGEN Match as a 1D vector).

Note that we need to know *guaranteed* non-matching addresses. These we
*know* can be done in parallel, whereas unknown or clashing addresses must
be done in-order and in series.

The non-matching 2D array of bits go directly into the SR Latch
cancellation signals of the corresponding Dependency Cell of the MDM on
which the AGEN Matcher is overlaid.

The cancellation results in the LD/ST dependencies, many of which were done
transitively, being rapidly dropped. Once any given row in the MDM is
entirely free of hazards it will result in the "readable" or "writable"
signal (now renamed loadable and storable) going HI, which can be used to
trigger the AGEN CU to proceed to the next phase: actual LD or actual ST.

LD will be held up a little bit longer because it has to write to a
regfile. This will be done in the usual way, as if this was a plain ALU, by
having a write dependency on the dest reg. ST does not need to write to a
register so didn't have a write dependency: thus when GoStore is fired the
FURegs Matrix is empty of dependencies.

I still have to put in some logic for exceptions, which will be done with
shadows. These will hold back the commit of the ST and also allow
cancellation of the instruction if there is a cache miss.

The shadow system is already in place so can just be plugged in.

Slowly this is coming together, it will soon be time to drop this into the
main unit test, create some pseudo LD/ST instructions and see what happens.


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