[libre-riscv-dev] vliw idea naming

[Luke Kenneth Casson Leighton]

On Mon, Jun 24, 2019 at 11:27 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> I want to read over all your svprefix changes a little more before I answer
> your questions.

they'll keep accumulating (at the end of each document).  i'm on this
full-time, got to get it done.

> the vliw idea sounds like a good idea, though I would call it a vector
> block or something like that

 yeah i like that. VBLOCK, VBL, VBLK for short.  i already use the
word "Block" to describe the "Register Block".

> -- it's much more similar to arm's thumb2 IT
> instruction (adds predicates for up to 4 following instructions) than
> traditional vliw, since the operations still appear to execute sequentially
> and the processor can internally reorder them.

 yes it's... hang on..
 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0338g/ch01s02s01.html

"Addition of a 16-bit IT instruction that enables 1 - 4 following
Thumb instructions to be conditional".

yyyeahh kiiinda, except it also adds, at the very beginning of the sequence:

 * the option of setting VL, MVL and SUBVL (as if they were actual
instructions, right there, right then)
 * the option of setting up Register "redirection" that was formerly

and the predicates do not *always* apply "conditionally", there are up
to 4 *registers* marked as "predicated", which, if used anywhere in
the next (80 + 16*0bNNN) bits, will be conditional.

so... kinda like thumb2 IT, but not exactly.  much longer (up to a
maximum of 11 RVC opcodes if no optional blocks are used, which is
kinda pointless but possible).

yes, the sequence of opcodes within the block *must* be sequential
just like any other RISC-V instructions.

all the prefixing is, is: an excuse to get the (full-format)
predication and register table entries into a compact "context".

if it was possible for branches to recover the context without
desperately searching backwards through the I-Cache, looking for where
the VBLOCK format started, it could be allowed to advance PC instead
of having to create a VLIWPC and advance that.

l.