[libre-riscv-dev] sv swizzle constants

[Jacob Lifshay]

On Tue, Jun 25, 2019, 12:48 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> Ok so a suite of constants (immediates) are needed, to be able to specify
> the permutations of up to 4 subvector elements, x y z w.
>
> That is 4 x 3 x 2 x 1 permutations which is 24 so 5 bits are needed to
> express them, per register.
>
it's actually 4 x 4 x 4 x 4, since repeats are allowed -- I even had a
repeat in the example for velswizzle.
For SVorig, swizzle should only be supported on mv -- supporting it on
everything will drastically increase pipeline complexity for every op --
similar to ARM putting the barrel shifter in every instruction -- not
necessary for the common case.
For SVprefix, I suggest using 8 or 12 immediate bits to encode that using a
dedicated opcode.
12 bits (3 per element) allows us to encode often-used constants as swizzle
inputs or the similar to LLVM's 2-input swizzle (select between options by
using x0 as rs2).
for the constants, I recommend:
4. +0
5. +1
6. -1
7. index of current subvector (int) / reserved (float)

the numbers are encoded using the eltype, so a swizzle using integer types
gets the values as integers and the float types gets the values as float
numbers.

index of current subvector works like:
VL = 4
velswizzle x32, x48, x0, SRCSVLEN=1, DESTSVLEN=4, ELTYPE=u64, elements=[+0,
+1, -1, index]

produces:
x32 = 0
x33 = 1
x34 = -1
x35 = 0

x36 = 0
x37 = 1
x38 = -1
x39 = 1

x40 = 0
x41 = 1
x42 = -1
x43 = 2

x44 = 0
x45 = 1
x46 = -1
x47 = 3