[libre-riscv-dev] sv swizzle constants

[Luke Kenneth Casson Leighton]

Ok so a suite of constants (immediates) are needed, to be able to specify
the permutations of up to 4 subvector elements, x y z w.

That is 4 x 3 x 2 x 1 permutations which is 24 so 5 bits are needed to
express them, per register.

That's a lot.

For only 3 permutations it is 3 x 2 x 1 so 6 which is only 3 bits.

My recomnendation is that we follow the trail of the VBLOCK Format and
create an 8 and 16 bit tabke fornat that is basically 3 + reg (5 bit) or 5
+ reg

Not sure what to do with the spare 6 bits in the 16 bit block format.

I *think* i can jam in an escape-code sequence into the VL/MAXVL/SUBVL
block in VBLOCK, or, if that doesn't work, use the bit currently allocated
to "mode" as an escape-sequence. 0 means 8 bit mode, 1 means "sorry have to
interpret the next 16 bits" and that would be what specs out further
encodings.

Or....

There is always the 192+ format, which is 0b111 in the length field.

Does the idea of a swizzle immediate table similar to the Reg one and Pred
one sound reasonable?

Same principle, "if register in opcode is in swizzle table, look up swizzle
immediate and apply it".

L.



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