[libre-riscv-dev] LD/ST address matcher

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jun 4 00:58:13 BST 2019

On Tuesday, June 4, 2019, Jacob Lifshay <programmerjake at gmail.com> wrote:

> another case we can't get around

The double negative is doing my head in :)

>  by allowing multiple simultaneous loads is
> drawing to multiple output textures simultaneously, a technique that allows
> expensive lighting calculations to be done once per visible pixel instead
> of once per rendered pixel.

And those are again aligned on regular boundaries, of what size?  Hmmm it
would be the screen (framebuffer) size, wouldn't it, by that point?

There is actually another potential trick: take some bits of the PHYSICAL
address to check against, as well as the virtual one.

I believe I saw this trick described somewhere in the RISCV manual.

With the physical pages being spread out pretty much randomly (assuming
gigapages aren't used), the extra PHYS bits effectively constitute the
equivalent of a hash.

However gigapages could well be used here, so, hmmmm

We need something that covers bits up to say 4MiB.  That's 9 extra bits -
12 to 21. 2^20 =1M, 2^22=4M.

So a VERY simple hash of 9 bits is viable.  Bear in mind its gate count
will be multiplied by 248(!) for a 4LD 4ST AGEN clash detection matrix.



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