[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=99

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
http://bugs.libre-riscv.org/attachment.cgi?id=17

radix-8 is on page 40, section 3.3.4, figure 3.20 on p41.

what's nice is: he really does a good job explaining.
figure 3.21 explains really clearly how a 3:2 CSA
is implemented.  figure 3.15 (p36) explains how
OTFC works.

r btw is the radix (base) - eq 3.15, 3.16.  took a
looong time to work this out.  

also, the VHDL is in the appendix.

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