[libre-riscv-dev] [Bug 94] implement load/store memory dependency matrix

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=94

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
    NLnet milestone|---                         |NLnet.2019.02

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

* the ALU-like LD/ST-capable CU's "request release" signal is now the direct
mirror-equivalent of "AGEN release".

* thus (ignoring the priority picker), we can AND the req_rel signal with the
"readable/writable" (now "loadable / storable"), this gives the "ENable"
signals to put the addresses into the AGEN match

* some of those will generate "clashes", some will not, however the results
will need to be ANDed with the "ENable" vector to determine which ones can drop
dependencies back at the MDM and which can *not* be dropped.  otherwise you
could accidentally drop "unknown" addresses.

* meanwhile, *only* those signals that (after AGEN clash detection) did not
match may go through to the CU to tell it that it can proceed to the next
phase: actually do the LD/ST read/write to memory.

* i *believe* that we still have to keep the MDM dependency around until such
time as the LD/ST has actually completed (or come back with a cache miss).  the
reason being that there may be new instructions which use the same address.

* only when the LD/ST is actually completed to memory can we drop both the Reg
DM Dep (in the case of LD) *and* the MDM Dep.

* special case: for ST we could have dropped the Reg DM Dep slightly early,
caveat: *not on a cache miss chance!*

-- 
You are receiving this mail because:
You are on the CC list for the bug.