[libre-riscv-dev] [Bug 94] New: implement load/store memory dependency matrix

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=94

            Bug ID: 94
           Summary: implement load/store memory dependency matrix
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-June/001725.html

a LOAD and STORE memory dependency matrix is needed.  must be multi-issue
capable i.e. must be capable of handling several LD/ST operations
simultaneously
and also be able to accept and process multiple LD/ST operations in a single
cycle.

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