[libre-riscv-dev] sv.setvl encoding

[Luke Kenneth Casson Leighton]

On Saturday, June 29, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> There are now 4 bits left in SVSTATE unused. That is *just* enough to
> increase all 4 of srcoffs destoffs vl and mvl by 1 bit.
>
> however the VLtyp in P64 and the VBLOCK equivalent these would have to
> stay at 6 bit, even 5 bit in some cases.
>

 https://libre-riscv.org/simple_v_extension/vblock_format_table/?updated

Turns out the VBLOCK VL prefix has 1 more bit than i expected.

A compressed version of 3 arg sv.setvl which can source VL from a reg, set
MVL as an immediate, and also get VL into a dest reg is so important i
think it is worth jamming in.

What do you think of the idea of using t0 or t1 as the VLdest reg, if bits
30-31 are 0b01?

I am really not a fan of hardcoding regs like this however it gets...
sonething.

The alternative is an RVC-like 3 bits per rs1, 3 per rd encoding.

What's thoughts there?

L.



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