[libre-riscv-dev] [Bug 93] add Cache-as-ram mode for boot

Samuel Falvo II sam.falvo at gmail.com
Wed Jun 5 22:39:41 BST 2019

Wow, this is very close to my idea of using preconfigured tags and
manual control over write-through and write-back features in the cache
hardware!  Good to know that prior art exists for that concept and is

On Wed, Jun 5, 2019 at 2:27 PM <bugzilla-daemon at libre-riscv.org> wrote:
> http://bugs.libre-riscv.org/show_bug.cgi?id=93
> --- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> mitch writes:
> BTW, the way I solved this in my ISA/Architecture; is to define an "Allocated"
> bit in the PTEs (My architecture comes out of reset with the MMU turned on
> and paging enabled--there is actually no means to disable the MMU).
> The Allocated PTE bit tells the cache hierarchy that this line will not be
> migrated
> outside of the caches. The line can migrate up from L2 to L1 or migrate down
> from L1 to L2 but is not allowed to migrate farther out than L2.
> So I can now use the memory of the caches as a place to store data while
> DRAM gets initialized, and configured, counted, bundled, and handed over
> to the OS later boot processes.
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Samuel A. Falvo II

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