[libre-riscv-dev] store computation unit
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Jun 1 21:25:41 BST 2019
On Sat, Jun 1, 2019 at 9:05 PM Mitchalsup <mitchalsup at aol.com> wrote:
> > ok. so, actually make the address computation its own unit
> > (particularly as it can be used as an ADD-immediate ALU), i would
> > prefer that as the graph's getting on the large side for this unit.
> I think what you are going to want to do is to treat the issue of memory refs
> as the issue of the AGEN and a simultaneous issue of the MEM access.
> The Go_Read for AGEN will make the corresponding MEM unit contend at
> the Memory picker for an access to the cache. The GO_MEM signal gates
> the address to the cache,...
okaaay so fire off access to the cache a cycle early, so that it
responds "ready" when the address is ready.
> > my mind wants to treat the address output as if it was an *actual*
> > register, to create effectively micro-code splitting the
> After adding some memory concurrency, you will want several of these
> address flip-flops so that you can have several outstanding cache misses.
> These address registers will be coupled to the memory dependency matrix
> so that register writes and memory stores remain in program order.
yes. the one with load-hit and store-hit-with-data. i _believe_ i
have those signals generated by the diagram (updated in the past few
hours to make it do LD _and_ ST - and ADD/SUB).
More information about the libre-riscv-dev