[libre-riscv-dev] SV Prefix questions
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Jun 26 06:10:21 BST 2019
On Wed, Jun 26, 2019 at 3:32 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> at the cost of needing us to have to spend a week, potentially
> longer, doing a full and comprehensive evaluation of pseudo-assembly,
> compared to riding off the back off a *lot* of work by a *lot* of
> extremely experienced people in the field of Vectorisation.
... plus, STATE is needed anyway. how else would it be possible to
make SVprefix instructions re-entrant, in order to deal with
exceptions/traps/interrupts in a sane fashion?
and if STATE is needed, it might as well be the same format as SV.
likewise SVprefix might as well follow the same rules as SV.
step, step, step, one logical progression after the other. any
deviation, anything "special", has to be:
* thought through
* specially documented
* implemented as special-cases
if they are both near-identical as possible, we have far less work to
do, and a lot less explaining to end-users.
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