[libre-riscv-dev] [Bug 106] New: pipeline early-in, early-out on concurrent function units

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat Jun 29 15:45:43 BST 2019


            Bug ID: 106
           Summary: pipeline early-in, early-out on concurrent function
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: ALU (including IEEE754 16/32/64-bit FPU)
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

the FP ALUs need to be re-useable for INT computation, by allowing
early-in (bypassing normalisation), getting at what would normally
be just the mantissa part of the pipeline, and jumping out.

whilst early-out is easy (due to the muxid), early-in may be challenging.
the simplest method, although it has the strong disadvantage of creating
unnecessary latency, is to just feed in the operands at the front of
the pipeline.

however, a timing-critical method of bringing the muxids from the later
stages up to the front (the Reservation Station) may also work.

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