[libre-riscv-dev] sv-prefix RVC

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Jun 30 10:46:04 BST 2019


the rule is: don't try to fit "part" of a standard scalar RISC-V
encoding, fit *all* of it, "prefixed".  this saves huge amounts of
time, both in trying to "invent" entirely new scalar ISA encodings, as
well as saving time *writing* those decoders *and* saving gates by
re-using the *existing* (scalar) decoder, and just "prefixing" them
with "vector context".

however - and this is a royal pain - even if two custom opcodes are
used for embedding RVC, there is still one bit missing that would
allow the full prefix of P48 to be deployed (unmodified, with one bit

the pain-in-the-neck is twin-predication.  we need to lose one bit
somewhere.  options:

* lose twin-predication entirely (not a fan)
* reduce the functionality of twin-predication (tpred 2-bit mode, only
providing a subset of the modes: lose inversion for example).
* reduce vew by 1 bit to only 1 bit (not a good option)
* lose one of the vectorisation modes (one reg is scalar-only or
vector-only).  given that this is LD/ST and C.MV it would mean
reducing the vector modes even further.
* use ISAMUX/ISANS to "page in" the RVC "op" bits.  only 3 options are
needed here (there are only 3 pages).
* use *another* MAJOR OPCODE for the extra bit.  (CUSTOM-0 == RVC page
0, CUSTOM-1 == RVC page 1, CUSTOM-2 == RVC page 3)

of all of the options that are "least good", using three out of four
of the major opcodes is one i prefer, because it gives the ability to
use the entire P48 encoding *unmodified*.  and there is plenty of
brownfield encoding space to play with.


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