[libre-riscv-dev] SV Prefix questions

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68


On Fri, Jun 21, 2019 at 8:57 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> https://libre-riscv.org/simple_v_extension/sv_prefix_proposal/#questions
>
> Needs some answers, when you have a moment Jacob, can you drop them into
> the page there?
>

this is how to "deal" with VL and MVL not being "permitted" to be set to
zero.  just jump (unconditionally) to the zero-testing point (a la while do
rather than do while).

i realise it may have implications: it's definitely different from RVV.
are there any important caveats that you can think of?

original example (DAXPY) at the "SIMD considered harmful" article also
contains the (near-exact) same RV32 vector code.
https://www.sigarch.org/simd-instructions-considered-harmful/

*     CSRvect1 = {type: F, key: a3, val: a3, elwidth: dflt}*














*     CSRvect2 = {type: F, key: a7, val: a7, elwidth: dflt}     CSRRWI MVL,
3          # sets MVL == **4** (not 3)     j zerotest             # in case
loop counter a0 already 0    loop:     CSRRW VL, t0, a0       # vl = t0 =
min(mvl, a0)     ld     a3, a1          # load 4 registers a3-6 from x
 slli   t1, t0, 3       # t1 = vl * 8 (in bytes)     ld     a7, a2
 # load 4 registers a7-10 from y     add    a1, a1, t1      # increment
pointer to x by vl*8     fmadd a7, a3, fa0, a7 # v1 += v0 * fa0 (y = a * x
+ y)     sub    a0, a0, t0      # n -= vl (t0)     st     a7, a2          #
store 4 registers a7-10 to y     add    a2, a2, t1      # increment pointer
to y by vl*8    zerotest:     bnez   a0, loop        # repeat if n != 0*