[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=99

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
we need to keep the FPDIV pipeline stage as short as possible:
RADIX-8 would be the preferred option.

this to reduce the number of Reservation Stations (Function Units)
needed to keep a Concurrent Computation Unit (aka "pipeline") fully
occupied and not cause freezing of the entire issue stage.  see here
for details:

http://bugs.libre-riscv.org/show_bug.cgi?id=101#c2

basically if we have a 24-stage pipeline (not unreasonable for
radix-2 divide) we need a staggering *TWENTY FOUR* Function Units
(src/result latch sets, plus 24 rows in the Dependency Matrices),
just to keep track of all the (potential) results.

bottom line: Radix-8 is, well, pretty high priority would be an
understatement :)

FP64 is just not a high priority (no need to be concerned about stalling,
there, we can even use the FSM version), it's FP32 that's the biggest issue
due to needing one FPDIV per pixel on 3D.

-- 
You are receiving this mail because:
You are on the CC list for the bug.