[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat Jun 29 10:38:01 BST 2019


--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this is what the stack looks like.  it looks complicated: it's not.
the work's "already done".

the entry-points for the INT-based DIV unit are in div0.py, div1.py and div2.py

the only reason for the existence of those three classes is purely to
deal with the fact that the data has to be converted on exit from the
pre-normalisation phase into the Q/REM DIV-chain, and also converted
on entry to the *post* normalisation phase.

div0.py deals with the "setup"
div1.py deals with one Q/Rem "step"
div2.py deals with the "exit"

if you can get an INT DIV radix-2 (or 4, or 8) unit up and running
in the next day or so, with appropriate parameterised classes that
do setup, step and exit, i can shoe-horn them in and we can see how
it goes.

scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData  ospec FPSCData
            StageChain: FPDIVSpecialCasesMod,

pipediv0 - FPDivStages(start=true) ispec FPSCData       ospec FPDivStage0Data
            StageChain: FPDivStage0Mod,

pipediv1 - FPDivStages()           ispec FPDivStage0Data ospec FPDivStage0Data
            StageChain: FPDivStage1Mod,

pipediv5 - FPDivStages(end=true    ispec FPDivStage0Data ospec FPAddStage1Data
            StageChain: FPDivStage1Mod,

normpack - FPNormToPack            ispec FPAddStage1Data ospec FPPackData
            StageChain: Norm1ModSingle,

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