[libre-riscv-dev] System-Wide Complexity Rant (was store computation unit)

[Samuel Falvo II]

On Wed, Jun 5, 2019 at 12:35 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>  worth pursuing. main barrier would be if it adversely affects
> performance or adds in too much latency.

The other option is pre-configured and locked cache tag CAMs, set so
that both write-through and write-back are turned off.  When SDRAM is
initialized, you can turn write-* on, perform a quick memory check to
make sure it works, and if so, release the CAMs to function as they
normally would.

-- 
Samuel A. Falvo II