[libre-riscv-dev] sv.setvl encoding

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Jun 29 06:06:24 BST 2019

On Fri, Jun 28, 2019 at 10:00 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Fri, Jun 28, 2019, 12:52 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
> > On Saturday, June 29, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > wrote:
> >
> > > There are now 4 bits left in SVSTATE unused. That is *just* enough to
> > > increase all 4 of srcoffs destoffs vl and mvl by 1 bit.
> > >
> > > however the VLtyp in P64 and the VBLOCK equivalent these would have to
> > > stay at 6 bit, even 5 bit in some cases.
> > >
> >
> >  https://libre-riscv.org/simple_v_extension/vblock_format_table/?updated
> >
> > Turns out the VBLOCK VL prefix has 1 more bit than i expected.
> >
> > A compressed version of 3 arg sv.setvl which can source VL from a reg, set
> > MVL as an immediate, and also get VL into a dest reg is so important i
> > think it is worth jamming in.
> >
> > What do you think of the idea of using t0 or t1 as the VLdest reg, if bits
> > 30-31 are 0b01?
> >
> > I am really not a fan of hardcoding regs like this however it gets...
> > sonething.
> >
> > The alternative is an RVC-like 3 bits per rs1, 3 per rd encoding.
> >
> > What's thoughts there?
> >
> I think the RVC encoding will probably be better, since it can encode more
> registers -- reducing effective register pressure, hopefully saving
> instructions to move values around.

 can you see if you can do the same thing with VLtyp in the P64 format?

> I think it would also be a good idea to have a 32-bit VBLOCK prefix that
> can encode larger MAXVL and the full range of registers.

 hmm... it's excessive / redundant, as you might as well just use
sv.setvl.  a 24-bit...  wait... you're suggesting a 32-bit *VBLOCK*
prefix or a 32-bit *VL* Block format?

because VBLOCK already has bit 15 which says "hello i am effectively a
32-bit thing because the next 16 bits are the VL Block".

if that bit is taken up to be a mandatory 32-bit format, it wastes 16
bits in cases where you don't need VL.

one other option here is to begin using the greater-than-192-bit prefix.

if you meant "after the 16 bit VBLOCK prefix, have the option to have
a *32 bit* VL Block spec", then you might as well just have a sv.setvl

> This avoids
> needing an extra 32-bit instruction before VBLOCK just to set VL.

 that's what the (optional) 16 bit VL Block is for.

> also, VBLOCK needs some way to not set VL since it may be part of a larger
> loop that already sets VL.

the VL Block is optional. bit 15 of the opcode prefix (vlset)
enables/disables it.


More information about the libre-riscv-dev mailing list