[libre-riscv-dev] sv.setvl encoding

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jun 28 13:59:52 BST 2019


on comp.arch, the discussion on the VBLOCK format got derailed (as it
does) around instruction count in ISAs.  the main point: multiply tiny
improvements of even 1% stack up.

so *sigh* yes, it looks like VL and MAXVL should be offset from 0.  i
don't like it, because it makes the possibility to cover up to 64 just
not possible in the VBLOCK format and the P64 format is already
truncated (not enough spare bits).  CSRRWI is out the window so that's

it's quite a big change, both to the spec and the simulator.


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