[libre-riscv-dev] uniform instruction format

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Jun 18 16:24:59 BST 2019

jacob, you saw the discussion on isa-dev, the use of the unused bit 2
in the 3-bit width field of LOAD-FP / STORE-FP?

unfortunately in the LOAD/STORE (integer) the same bit is used to
indicate "signed" or "unsigned".  i think this was why, 8 months ago,
i removed the various strided-etc. variants and just went with "plain
unit stride or indexed", based on whether srcbase was vector / scalar.

btw, can you remind me why sub-vector exists (at all), again?  am i
correct in thinking that effectively its only purpose is not to act as
a multipler on VLEN, it's to multiply the reach (scope) of each of the
*predicate* bits by the sub-vector length, isn't it?


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