[libre-riscv-dev] uniform instruction format

[Jacob Lifshay]

On Sun, Jun 16, 2019 at 11:24 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> jacob, you missed some questions, which are important to resolve.  going
> through the pseudo-code, and also through the RV spec, the format of
> RV48-I-type seems wrong.  the pseudo-code says that it should match exactly
> with RV32-I-Type, which it does not.
>
> also can you clarify if the other potential error that i spotted is or is
> not correct?
the P48FI encoding is correct, the fmt field is the lower 2 bits of
funct7. The underlying format is actually I-type, but the entire
immediate field is used for opcode.
for an example, see the encoding of fsqrt.s on page 66 of Volume I:
RISC-V Unprivileged ISA V20181221-Public-Review-draft.
bit fields:
31:27 -- funct5 (more opcode)
26:25 -- fmt (set to S which is 00)
24:20 -- rs2 (0 for fsqrt.s, which is what makes it I-type instead of R-type)
19:15 -- rs1
14:12 -- rm
11:7 -- rd
6:0 -- opcode
>
> l.
>
> +---------------+-------------+-------+----------+----------+--------+----------+--------+
> | Encoding      | 47:43       | 42:41 | 40:36    | 35:31    | 30:28  |
> 27:23    | 22:18  |
> +---------------+-------------+-------+----------+----------+--------+----------+--------+
> | RV32 Encoding | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7
>     | 6:2    |
> +---------------+-------------+-------+----------+----------+--------+----------+--------+
> | P48FI-type    | funct7[6:2] | fmt   | funct5   | rs1[4:0] | rm     |
> rd[4:0]  | opcode |
> +---------------+-------------+-------+----------+----------+--------+----------+--------+
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