[libre-riscv-dev] uniform instruction format

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Mon, Jun 17, 2019 at 8:55 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> On Sun, Jun 16, 2019 at 11:24 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > jacob, you missed some questions, which are important to resolve.  going
> > through the pseudo-code, and also through the RV spec, the format of
> > RV48-I-type seems wrong.  the pseudo-code says that it should match exactly
> > with RV32-I-Type, which it does not.
> >
> > also can you clarify if the other potential error that i spotted is or is
> > not correct?
> the P48FI encoding is correct, the fmt field is the lower 2 bits of
> funct7. The underlying format is actually I-type, but the entire
> immediate field is used for opcode.
> for an example, see the encoding of fsqrt.s on page 66 of Volume I:
> RISC-V Unprivileged ISA V20181221-Public-Review-draft.
> bit fields:
> 31:27 -- funct5 (more opcode)
> 26:25 -- fmt (set to S which is 00)
> 24:20 -- rs2 (0 for fsqrt.s, which is what makes it I-type instead of R-type)
> 19:15 -- rs1
> 14:12 -- rm
> 11:7 -- rd
> 6:0 -- opcode

turning the horizontal table entry for P48FI-type around:

31:27   | funct7[6:2] <---- this should be funct5
26:25:  fmt
24:20  funct5 <---- this is the one that's not correctly listed
19:15 rs1[4:0]
14:12 rm
11:7 rd[4:0]
6:0 opcode

once that's corrected, it's back to looking just like RV32-I-Type,
just with the special option "rs2=0" to specify FSQRT.

btw i enabled rst on the libre-riscv.org ikiwiki and put the document here:
https://libre-riscv.org/simple_v_extension/sv_prefix_proposal/

l.