[libre-riscv-dev] uniform instruction format

[Luke Kenneth Casson Leighton]

On Mon, Jun 17, 2019 at 2:52 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> On Sun, Jun 16, 2019 at 7:16 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > oh, btw, jacob: twin-predication is *really* important to fit into the
> > 48/64-bit format.  having 3 4 5 or 6 predication registers is
>
>  damnit, twin-predication needs two VStarts - one for the first
> register element offset, and one for the second.  that blows the
> 64-bit budget, making the 64 bit format internal only.

 correction: the first 2 bits of VL are in vtp5/vitp6/vitp7, therefore
the remaining 4 bits are good to put into the 16-bit table (that takes
48-bit up to 64-bit).

 4 + 6 + 6 = 16.
 VL[5:2] + VStart1[5:0] + VStart2[5:0]

l.