[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=99

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #16)
> one other thing, the pipeline code needs to support one class having
> multiple stages inside it,

 if you can wrap them with a StageChain and create a separate class
 that has multiple stages because *StageChain* separates the multiple
 stages, that would be better.

 however it is not strictly necessary to do that: there's nothing
 to stop an individual stage having 2+ clock latency.

 the only thing is: anything that is not full combinatorial *cannot*
 then later be wrapped with StageChain, it *has* to be embedded in
 a full pipe class.

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