[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=99

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=ieee754fpu.git;a=commitdiff;h=2789fb65d1d70e70d45c0e2506dfc18d13939bb1

src/ieee754/fpdiv/divstages.py done
test_fpdiv_pipe.py done
pipeline.py done

all cookie-cut.

div0.py is an "example" class, again cookie-cut.  FPDIVStage0Data
is where the incoming data (from pre-normalisation) gets turned
into "first stage stuff that contains intermediary results
such as Q and R".

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