[libre-riscv-dev] store computation unit
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Jun 20 16:56:30 BST 2019
On Thursday, June 20, 2019, Mitchalsup <mitchalsup at aol.com> wrote:
We have the equations::
> Readable = ANY( operand<0:31> &
> ~GlobalWritePending<0:31> )
> Forwardable = ANY( FUwriteDependent<0:15> & RequestRelease<0:15>
> Executable = Readable | Forwardable
> Where executable takes no more gates of delay that Readable or
> Forwardable; and adds only 3 real gates to the calculation of all 3
> An Operand is executable if its operand can be found as a result in
> FUresult[i] or it if is current in RF[k].
> Where we know k from the instruction and we know i from the write
> dependencies at issue.
> If all operands are executable so is the instruction.
> If you pick an executable instruction you read out the registers to be
> read and you read out the FU who
> can write this register and you use Readable and Forwardable to decide
> whether to get the operand from the result vector or from the register file.
> This enables one to begin executing an instruction from the timing of
> RequestRelease of instructions it is RAW dependent upon and not have to
> wait for GoWrite. If you happen to begin such an instruction, you have to
> go get its result from the result vector at the end of the calculation
This is the bit that my brain has been focussing on, independently (hence
why I was delighted to learn that you have been focussing on a different
area of the same space).
> Also note: an unconditional branch does not cast a shadow!
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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