[libre-riscv-dev] sv.setvl encoding

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jun 28 07:37:04 BST 2019

On Fri, Jun 28, 2019 at 7:27 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> Actually, I think that STATE can be refactored a bit to work just fine
> with longer VL values:
> So, here's the list of STATE fields from the current version of the SV spec:
> * MVL -- keep
> * VL -- keep
> * destoffs - the destination element offset of the current parallel
>   instruction being executed
>   -- keep
> * srcoffs - for twin-predication, the source element offset as well
>   -- keep, though can be removed since it can be recomputed (slowly)

 i said already: i don't like it.  the algorithm itself is complex
(did the evaluation a couple days ago), in what is already a massively
ambitious project.

 that adds both time and complexity.

> * svsrcoffs - for twin-predication, the subvector source element offset
>   as well
>   -- remove. not needed since predicates operate on whole subvectors,

ah!  good point!  well spotted.

> Adding them all together, we get VLLEN * 4 + 4. The largest value of
> VLLEN that can be used on RV32 is 7. For RV64, VLLEN can be further
> increased to 15, which is more than sufficient.

 next to consider is P64, as well as VBLOCK.  these definitely won't
fit, and i'm not ok with VBLOCK's VLtyp needing to fit into 32 bits
(or 24).  not for this version, not at this late stage.

> RV128:
> bits 64-127: reserved (must be 0)

 RV128 is *completely* off the table at this late stage.

> >  the MAXVL field fits across the rs2 field rather than the top
> > immediate bits (normally a funct5/6/7).  which would complicate
> > brownfield encoding that wanted an rs2.
> it's the opcode and funct7 that are actually used to determine the
> instruction for almost all RISC-V instructions, therefore, I think we
> should use the lower bits of the immediate in I-type to encode MAXVL.
> This also has the benefit of simple extension of VL/MAXVL since the
> bits immediately above the MAXVL field aren't used. If a new
> instruction wants to be able to use rs2, it simply uses the encoding
> with bit 31 set, which already indicates that rs2 is wanted in the V
> extension.

yep i like that logic, let's go with VLMAX in 30:20.


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