[libre-riscv-dev] VL concept

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jun 20 19:53:52 BST 2019

Hang on, I just had a thought, based on the VLIW problem of defining VL for
a block.

Instead of setting VL at the start of a block, conplicating CSRRW, why not
have a CSR that says, "register N *is* VL from now on".

That way it is not necessary to store the CSR Vstart as context, because it
*is* the register that is already *being* context switched.

The only issue is, if you want to set VL to an immediate, it takes 2
instructions to do so.

So an alternative is to have 2 CSRRWIs one that sets the register to be
used as VL, the other sets VL as an immediate.

The immediate _would_ need to be context switch saved.

It could be 6 bits, just like in the VLIW VL Block.

Bit 0: imm or reg mode.
BITS 1 to 5: imm 0 to 31 in imm mode, regnum otherwise.

I like this a lot more than the current CSR VL.

Twin predication however needs *two* indices. Therefore *two* registers.

Am I getting things mixed up, here? Need some help going over it properly.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the libre-riscv-dev mailing list