[libre-riscv-dev] store computation unit

[Luke Kenneth Casson Leighton]

ok so i have a preliminary unit test up and running, with the two
memory-based dependency matrices.

* the first matrix is based directly on FU-Regs.  names changed to
protect the guilty: the unary reg#s became unary FU#s, dest_reg_i
became ld_fu_i, src2 got deleted, src2_reg_i became st_fu_i.

* the second matrix is the one from section 11.4.12, which
encapsulates the load-holds-store and store-holds-load rules.

and... i realised i've been a bit of an idiot.  took me a few days to
recognise it.

i'd *assumed* that the second matrix is equivalent to the FU-FU one,
which from explorations a few weeks back we learned the hard way it
expresses result-interdependence.  thus, i could create the first
matrix on FU-Regs.

wark-wark...

the clue should have been that FU-Regs "forward progress" comes from
ORing the read register dependencies with the *write* function-unit
latch information, which is precisely what the second
(memory-dependency) matrix does (except read-->store and
write-->load).

the second clue should have been that just as the register
dependencies are *dropped*, so are the memory dependencies, and, only
when cleared, do we get an "all clear" signal (a NOR).

so... sigh... i'm now going to try copying and adapting the FU-FU
matrix instead, and connect that to the MemDep one, and see what
happens.

l.