[libre-riscv-dev] sv spike simulator

[Luke Kenneth Casson Leighton]

On Thu, Jun 27, 2019 at 12:54 PM Jacob Lifshay <programmerjake at gmail.com> wrote:

> yay!

 :)

 https://git.libre-riscv.org/?p=riscv-tests.git;a=blob;f=isa/rv64ui/sv_addi_predicated_subvl.S;h=ea30797a70675e3fabd73ee66b7ee68d470aca58;hb=refs/heads/sv

and that one's good too.  so predication, with inversion and/or
zeroing, when SUBVL=2 and VL=2, works fine. can possibly make that a
longer test: by setting elwidth to 8 i was able to jam in 4 numbers
into a single 32-bit value.

still early days, i'd missed this for example:

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 3d6d2e9..988cfca 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -136,9 +136,7 @@ unsigned int sv_proc_t::remap(reg_spec_t const&
spec, bool pred)
     // register offset is computed.  if subvl is active, it's a multiplier
     //fprintf(stderr, "remap %ld subvl %ld offs %ld subo %ld\n",
     //                spec.reg, p->get_state()->sv().subvl, offs, subo);
-    if (!pred) {
-        offs = offs * p->get_state()->sv().subvl + subo;
-    }
+    offs = offs * p->get_state()->sv().subvl + subo;
     sv_shape_t *shape = p->get_state()->get_shape(spec.reg, pred);
     if (shape == NULL) {
         return offs;

l.