January 2020 Archives by author

Messages sorted by: [ thread ] [ subject ] [ date ]
More info on this list...

Starting: Wed Jan 1 01:02:00 GMT 2020
Ending: Fri Jan 31 23:36:22 GMT 2020
Messages: 449

[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal lkcl .
[libre-riscv-dev] Rust over C/C++ Hendrik Boom
[libre-riscv-dev] Rust over C/C++ Hendrik Boom
[libre-riscv-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Hendrik Boom
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed Hendrik Boom
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Hendrik Boom
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Hendrik Boom
[libre-riscv-dev] PowerISA, NLNet grants Hendrik Boom
[libre-riscv-dev] POWER / RV dual interoperability Hendrik Boom
[libre-riscv-dev] Why The Dual ISA Hendrik Boom
[libre-riscv-dev] Adding Onboarding Instructions Hendrik Boom
[libre-riscv-dev] Needed standard cell development for libre SOC Jean-Paul Chaput
[libre-riscv-dev] formal proof of the conditions where smaller fp ops can be emulated by larger fp ops James Cloos
[libre-riscv-dev] [Mesa-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Jason Ekstrand
[libre-riscv-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Jason Ekstrand
[libre-riscv-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Jason Ekstrand
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Immanuel, Yehowshua U
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Immanuel, Yehowshua U
[libre-riscv-dev] Rust over C/C++ Immanuel, Yehowshua U
[libre-riscv-dev] Rust over C/C++ Immanuel, Yehowshua U
[libre-riscv-dev] Rust over C/C++ Immanuel, Yehowshua U
[libre-riscv-dev] Beginning Steps and Deadlines Immanuel, Yehowshua U
[libre-riscv-dev] Rust over C/C++ Immanuel, Yehowshua U
[libre-riscv-dev] Beginning Steps and Deadlines Immanuel, Yehowshua U
[libre-riscv-dev] Beginning Steps and Deadlines Immanuel, Yehowshua U
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Immanuel, Yehowshua U
[libre-riscv-dev] Possible nMigen Milestone? Immanuel, Yehowshua U
[libre-riscv-dev] Possible nMigen Milestone? Immanuel, Yehowshua U
[libre-riscv-dev] Possible nMigen Milestone? Immanuel, Yehowshua U
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Immanuel, Yehowshua U
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net Immanuel, Yehowshua U
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net Immanuel, Yehowshua U
[libre-riscv-dev] Why The Dual ISA Immanuel, Yehowshua U
[libre-riscv-dev] Why The Dual ISA Immanuel, Yehowshua U
[libre-riscv-dev] Why The Dual ISA Immanuel, Yehowshua U
[libre-riscv-dev] Why The Dual ISA Immanuel, Yehowshua U
[libre-riscv-dev] Why The Dual ISA Immanuel, Yehowshua U
[libre-riscv-dev] Why The Dual ISA Immanuel, Yehowshua U
[libre-riscv-dev] openrisc1200 Immanuel, Yehowshua U
[libre-riscv-dev] openrisc1200 Immanuel, Yehowshua U
[libre-riscv-dev] openrisc1200 Immanuel, Yehowshua U
[libre-riscv-dev] openrisc1200 Immanuel, Yehowshua U
[libre-riscv-dev] Adding Onboarding Instructions Immanuel, Yehowshua U
[libre-riscv-dev] Joining the Mailing List Immanuel, Yehowshua U
[libre-riscv-dev] HDL workflow page Immanuel, Yehowshua U
[libre-riscv-dev] Some general instruction ideas Immanuel, Yehowshua U
[libre-riscv-dev] Some general instruction ideas Immanuel, Yehowshua U
[libre-riscv-dev] Some general instruction ideas Immanuel, Yehowshua U
[libre-riscv-dev] Name change from Libre-RISCV to Libre-SOC Immanuel, Yehowshua U
[libre-riscv-dev] Adding Members page Immanuel, Yehowshua U
[libre-riscv-dev] Adding Members page Immanuel, Yehowshua U
[libre-riscv-dev] Name change from Libre-RISCV to Libre-SOC Immanuel, Yehowshua U
[libre-riscv-dev] new / additional domain Immanuel, Yehowshua U
[libre-riscv-dev] new / additional domain Immanuel, Yehowshua U
[libre-riscv-dev] [Libre-silicon-devel] [OT only slightly] STEAM Camp OpenSourceEcology 22jan2020 for 9 days Marcin Jakubowski
[libre-riscv-dev] Some general instruction ideas Lauri Kasanen
[libre-riscv-dev] Some general instruction ideas Lauri Kasanen
[libre-riscv-dev] HDL workflow page Lauri Kasanen
[libre-riscv-dev] [Libre-silicon-devel] [OT only slightly] STEAM Camp OpenSourceEcology 22jan2020 for 9 days David Lanzendörfer
[libre-riscv-dev] [Libre-silicon-devel] [OT only slightly] STEAM Camp OpenSourceEcology 22jan2020 for 9 days David Lanzendörfer
[libre-riscv-dev] meeting with libre soc team, questions Michiel Leenaars
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] Rust over C/C++ Luke Kenneth Casson Leighton
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] Rust over C/C++ Luke Kenneth Casson Leighton
[libre-riscv-dev] Beginning Steps and Deadlines Luke Kenneth Casson Leighton
[libre-riscv-dev] Beginning Steps and Deadlines Luke Kenneth Casson Leighton
[libre-riscv-dev] Beginning Steps and Deadlines Luke Kenneth Casson Leighton
[libre-riscv-dev] Rust over C/C++ Luke Kenneth Casson Leighton
[libre-riscv-dev] Beginning Steps and Deadlines Luke Kenneth Casson Leighton
[libre-riscv-dev] Beginning Steps and Deadlines Luke Kenneth Casson Leighton
[libre-riscv-dev] Beginning Steps and Deadlines Luke Kenneth Casson Leighton
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] Possible nMigen Milestone? Luke Kenneth Casson Leighton
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] Possible nMigen Milestone? Luke Kenneth Casson Leighton
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] Possible nMigen Milestone? Luke Kenneth Casson Leighton
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] Possible nMigen Milestone? Luke Kenneth Casson Leighton
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Luke Kenneth Casson Leighton
[libre-riscv-dev] introduction to Formal Mathematical Proof team Luke Kenneth Casson Leighton
[libre-riscv-dev] introduction to Formal Mathematical Proof team Luke Kenneth Casson Leighton
[libre-riscv-dev] introduction to Formal Mathematical Proof team Luke Kenneth Casson Leighton
[libre-riscv-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Luke Kenneth Casson Leighton
[libre-riscv-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Luke Kenneth Casson Leighton
[libre-riscv-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Luke Kenneth Casson Leighton
[libre-riscv-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Luke Kenneth Casson Leighton
[libre-riscv-dev] Needed standard cell development for libre SOC Luke Kenneth Casson Leighton
[libre-riscv-dev] Needed standard cell development for libre SOC Luke Kenneth Casson Leighton
[libre-riscv-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Luke Kenneth Casson Leighton
[libre-riscv-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed Luke Kenneth Casson Leighton
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Luke Kenneth Casson Leighton
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Luke Kenneth Casson Leighton
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Luke Kenneth Casson Leighton
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Luke Kenneth Casson Leighton
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] POWER / RV dual interoperability Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net Luke Kenneth Casson Leighton
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net Luke Kenneth Casson Leighton
[libre-riscv-dev] Why The Dual ISA Luke Kenneth Casson Leighton
[libre-riscv-dev] Why The Dual ISA Luke Kenneth Casson Leighton
[libre-riscv-dev] Why The Dual ISA Luke Kenneth Casson Leighton
[libre-riscv-dev] Why The Dual ISA Luke Kenneth Casson Leighton
[libre-riscv-dev] Why The Dual ISA Luke Kenneth Casson Leighton
[libre-riscv-dev] Why The Dual ISA Luke Kenneth Casson Leighton
[libre-riscv-dev] openrisc1200 Luke Kenneth Casson Leighton
[libre-riscv-dev] openrisc1200 Luke Kenneth Casson Leighton
[libre-riscv-dev] openrisc1200 Luke Kenneth Casson Leighton
[libre-riscv-dev] Joining the Mailing List Luke Kenneth Casson Leighton
[libre-riscv-dev] test Luke Kenneth Casson Leighton
[libre-riscv-dev] openrisc1200 Luke Kenneth Casson Leighton
[libre-riscv-dev] Adding Onboarding Instructions Luke Kenneth Casson Leighton
[libre-riscv-dev] Adding Onboarding Instructions Luke Kenneth Casson Leighton
[libre-riscv-dev] Michael - New Member Luke Kenneth Casson Leighton
[libre-riscv-dev] making a Request for Payment Luke Kenneth Casson Leighton
[libre-riscv-dev] Adding Onboarding Instructions Luke Kenneth Casson Leighton
[libre-riscv-dev] making a Request for Payment Luke Kenneth Casson Leighton
[libre-riscv-dev] making a Request for Payment Luke Kenneth Casson Leighton
[libre-riscv-dev] making a Request for Payment Luke Kenneth Casson Leighton
[libre-riscv-dev] Unsigned datatypes needed in sv2nmigen Luke Kenneth Casson Leighton
[libre-riscv-dev] making a Request for Payment Luke Kenneth Casson Leighton
[libre-riscv-dev] Michael - New Member Luke Kenneth Casson Leighton
[libre-riscv-dev] HDL workflow page Luke Kenneth Casson Leighton
[libre-riscv-dev] HDL workflow page Luke Kenneth Casson Leighton
[libre-riscv-dev] HDL workflow page Luke Kenneth Casson Leighton
[libre-riscv-dev] HDL workflow page Luke Kenneth Casson Leighton
[libre-riscv-dev] HDL workflow page Luke Kenneth Casson Leighton
[libre-riscv-dev] Some general instruction ideas Luke Kenneth Casson Leighton
[libre-riscv-dev] need help on working out a partitioned "eq" Luke Kenneth Casson Leighton
[libre-riscv-dev] Adding Members page Luke Kenneth Casson Leighton
[libre-riscv-dev] Name change from Libre-RISCV to Libre-SOC Luke Kenneth Casson Leighton
[libre-riscv-dev] Name change from Libre-RISCV to Libre-SOC Luke Kenneth Casson Leighton
[libre-riscv-dev] HDL workflow page Luke Kenneth Casson Leighton
[libre-riscv-dev] new / additional domain Luke Kenneth Casson Leighton
[libre-riscv-dev] new / additional domain Luke Kenneth Casson Leighton
[libre-riscv-dev] need help on working out a partitioned "eq" Luke Kenneth Casson Leighton
[libre-riscv-dev] new / additional domain Luke Kenneth Casson Leighton
[libre-riscv-dev] HDL workflow page Luke Kenneth Casson Leighton
[libre-riscv-dev] Wishbone Luke Kenneth Casson Leighton
[libre-riscv-dev] new / additional domain Luke Kenneth Casson Leighton
[libre-riscv-dev] architecture page Luke Kenneth Casson Leighton
[libre-riscv-dev] architecture page Luke Kenneth Casson Leighton
[libre-riscv-dev] architecture page Luke Kenneth Casson Leighton
[libre-riscv-dev] Wishbone Arbiter Luke Kenneth Casson Leighton
[libre-riscv-dev] new / additional domain Luke Kenneth Casson Leighton
[libre-riscv-dev] Adding Members page Luke Kenneth Casson Leighton
[libre-riscv-dev] new / additional domain Luke Kenneth Casson Leighton
[libre-riscv-dev] new / additional domain Luke Kenneth Casson Leighton
[libre-riscv-dev] HDL workflow page Luke Kenneth Casson Leighton
[libre-riscv-dev] Wishbone Arbiter Luke Kenneth Casson Leighton
[libre-riscv-dev] HDL workflow page Luke Kenneth Casson Leighton
[libre-riscv-dev] Wishbone Arbiter Luke Kenneth Casson Leighton
[libre-riscv-dev] HDL workflow page Luke Kenneth Casson Leighton
[libre-riscv-dev] nlnet rfps Luke Kenneth Casson Leighton
[libre-riscv-dev] Task splitting Luke Kenneth Casson Leighton
[libre-riscv-dev] bugzilla budget tracking Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 130] FMIN/MAX needed Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 130] FMIN/MAX needed Luke Kenneth Casson Leighton
[libre-riscv-dev] RISC-V extension development mailing lists now public Luke Kenneth Casson Leighton
[libre-riscv-dev] formal proof of the conditions where smaller fp ops can be emulated by larger fp ops Luke Kenneth Casson Leighton
[libre-riscv-dev] fosdem2020 Luke Kenneth Casson Leighton
[libre-riscv-dev] ieee754 formal proofs for fsgnj and fmax Luke Kenneth Casson Leighton
[libre-riscv-dev] fosdem2020 Luke Kenneth Casson Leighton
[libre-riscv-dev] meeting with libre soc team, questions Luke Kenneth Casson Leighton
[libre-riscv-dev] meeting with libre soc team, questions Luke Kenneth Casson Leighton
[libre-riscv-dev] meeting with libre soc team, questions Luke Kenneth Casson Leighton
[libre-riscv-dev] Rust over C/C++ Jacob Lifshay
[libre-riscv-dev] Rust over C/C++ Jacob Lifshay
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Jacob Lifshay
[libre-riscv-dev] Rust over C/C++ Jacob Lifshay
[libre-riscv-dev] Beginning Steps and Deadlines Jacob Lifshay
[libre-riscv-dev] Beginning Steps and Deadlines Jacob Lifshay
[libre-riscv-dev] Beginning Steps and Deadlines Jacob Lifshay
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Jacob Lifshay
[libre-riscv-dev] Yehowshua - Interested in open GPU dev Jacob Lifshay
[libre-riscv-dev] Possible nMigen Milestone? Jacob Lifshay
[libre-riscv-dev] Rust over C/C++ Jacob Lifshay
[libre-riscv-dev] introduction to Formal Mathematical Proof team Jacob Lifshay
[libre-riscv-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Jacob Lifshay
[libre-riscv-dev] [Mesa-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Jacob Lifshay
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed Jacob Lifshay
[libre-riscv-dev] [Mesa-dev] NLNet Funded development of a software/hardware MESA driver for the Libre GPGPU Jacob Lifshay
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed Jacob Lifshay
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Jacob Lifshay
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Jacob Lifshay
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Jacob Lifshay
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Jacob Lifshay
[libre-riscv-dev] PowerISA, NLNet grants Jacob Lifshay
[libre-riscv-dev] PowerISA, NLNet grants Jacob Lifshay
[libre-riscv-dev] PowerISA, NLNet grants Jacob Lifshay
[libre-riscv-dev] Why The Dual ISA Jacob Lifshay
[libre-riscv-dev] Why The Dual ISA Jacob Lifshay
[libre-riscv-dev] Why The Dual ISA Jacob Lifshay
[libre-riscv-dev] openrisc1200 Jacob Lifshay
[libre-riscv-dev] openrisc1200 Jacob Lifshay
[libre-riscv-dev] Adding Onboarding Instructions Jacob Lifshay
[libre-riscv-dev] openrisc1200 Jacob Lifshay
[libre-riscv-dev] Joining the Mailing List Jacob Lifshay
[libre-riscv-dev] Michael - New Member Jacob Lifshay
[libre-riscv-dev] making a Request for Payment Jacob Lifshay
[libre-riscv-dev] making a Request for Payment Jacob Lifshay
[libre-riscv-dev] HDL workflow page Jacob Lifshay
[libre-riscv-dev] HDL workflow page Jacob Lifshay
[libre-riscv-dev] Some general instruction ideas Jacob Lifshay
[libre-riscv-dev] need help on working out a partitioned "eq" Jacob Lifshay
[libre-riscv-dev] Some general instruction ideas Jacob Lifshay
[libre-riscv-dev] Name change from Libre-RISCV to Libre-SOC Jacob Lifshay
[libre-riscv-dev] new / additional domain Jacob Lifshay
[libre-riscv-dev] new / additional domain Jacob Lifshay
[libre-riscv-dev] Adding Members page Jacob Lifshay
[libre-riscv-dev] new / additional domain Jacob Lifshay
[libre-riscv-dev] new / additional domain Jacob Lifshay
[libre-riscv-dev] new / additional domain Jacob Lifshay
[libre-riscv-dev] Wishbone Arbiter Jacob Lifshay
[libre-riscv-dev] Wishbone Arbiter Jacob Lifshay
[libre-riscv-dev] Wishbone Arbiter Jacob Lifshay
[libre-riscv-dev] HDL workflow page Jacob Lifshay
[libre-riscv-dev] Task splitting Jacob Lifshay
[libre-riscv-dev] bugzilla budget tracking Jacob Lifshay
[libre-riscv-dev] RISC-V extension development mailing lists now public Jacob Lifshay
[libre-riscv-dev] formal proof of the conditions where smaller fp ops can be emulated by larger fp ops Jacob Lifshay
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal MitchAlsup
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Mitchalsup
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Mitchalsup
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Mitchalsup
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Mitchalsup
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Mitchalsup
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Mitchalsup
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal Mitchalsup
[libre-riscv-dev] HDL workflow page Michael Nolan
[libre-riscv-dev] HDL workflow page Michael Nolan
[libre-riscv-dev] Wishbone Arbiter Michael Nolan
[libre-riscv-dev] new / additional domain Michael Pham
[libre-riscv-dev] PowerISA, NLNet grants Tobias Platen
[libre-riscv-dev] PowerISA, NLNet grants Tobias Platen
[libre-riscv-dev] PowerISA, NLNet grants Tobias Platen
[libre-riscv-dev] Adding Onboarding Instructions Tobias Platen
[libre-riscv-dev] making a Request for Payment Tobias Platen
[libre-riscv-dev] making a Request for Payment Tobias Platen
[libre-riscv-dev] making a Request for Payment Tobias Platen
[libre-riscv-dev] making a Request for Payment Tobias Platen
[libre-riscv-dev] making a Request for Payment Tobias Platen
[libre-riscv-dev] making a Request for Payment Tobias Platen
[libre-riscv-dev] making a Request for Payment Tobias Platen
[libre-riscv-dev] Unsigned datatypes needed in sv2nmigen Tobias Platen
[libre-riscv-dev] Wishbone Tobias Platen
[libre-riscv-dev] Wishbone Tobias Platen
[libre-riscv-dev] architecture page Tobias Platen
[libre-riscv-dev] Wishbone Arbiter Tobias Platen
[libre-riscv-dev] architecture page Tobias Platen
[libre-riscv-dev] [Libre-silicon-devel] [OT only slightly] STEAM Camp OpenSourceEcology 22jan2020 for 9 days Hagen SANKOWSKI
[libre-riscv-dev] [Bug 153] Top-level for NLNet 2019.10 ASIC Cell Libraries Project. Staf Verhaegen
[libre-riscv-dev] Needed standard cell development for libre SOC Staf Verhaegen
[libre-riscv-dev] [Bug 153] Top-level for NLNet 2019.10 ASIC Cell Libraries Project. Staf Verhaegen
[libre-riscv-dev] Needed standard cell development for libre SOC Staf Verhaegen
[libre-riscv-dev] [Bug 153] Top-level for NLNet 2019.10 ASIC Cell Libraries Project. Staf Verhaegen
[libre-riscv-dev] Needed standard cell development for libre SOC Staf Verhaegen
[libre-riscv-dev] PowerISA, NLNet grants Staf Verhaegen
[libre-riscv-dev] Wishbone Staf Verhaegen
[libre-riscv-dev] fosdem2020 Staf Verhaegen
[libre-riscv-dev] meeting with libre soc team, questions Staf Verhaegen
[libre-riscv-dev] Why The Dual ISA Adam Van Ymeren
[libre-riscv-dev] Why The Dual ISA Adam Van Ymeren
[libre-riscv-dev] Why The Dual ISA Adam Van Ymeren
[libre-riscv-dev] openrisc1200 Adam Van Ymeren
[libre-riscv-dev] openrisc1200 Adam Van Ymeren
[libre-riscv-dev] openrisc1200 Adam Van Ymeren
[libre-riscv-dev] Yehowshua - Interested in open GPU dev whygee at f-cpu.org
[libre-riscv-dev] Possible nMigen Milestone? whygee at f-cpu.org
[libre-riscv-dev] [Bug 153] Top-level for NLNet 2019.10 ASIC Cell Libraries Project. whygee at f-cpu.org
[libre-riscv-dev] Design for test methodologies whygee at f-cpu.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed whygee at f-cpu.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed whygee at f-cpu.org
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal whygee at f-cpu.org
[libre-riscv-dev] PowerISA, NLNet grants whygee at f-cpu.org
[libre-riscv-dev] PowerISA, NLNet grants whygee at f-cpu.org
[libre-riscv-dev] PowerISA, NLNet grants whygee at f-cpu.org
[libre-riscv-dev] PowerISA, NLNet grants whygee at f-cpu.org
[libre-riscv-dev] PowerISA, NLNet grants whygee at f-cpu.org
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net whygee at f-cpu.org
[libre-riscv-dev] PowerISA, NLNet grants& In-Reply-To=<CAPweEDwwxZnij4WO5EQ1Gva6m24++yhNbpr4L6XkdF=g7gWm3Q at mail.gmail.com>" title=" PowerISA, NLNet grants">lkcl at lkcl.net whygee at f-cpu.org
[libre-riscv-dev] Why The Dual ISA whygee at f-cpu.org
[libre-riscv-dev] openrisc1200 whygee at f-cpu.org
[libre-riscv-dev] HDL workflow page whygee at f-cpu.org
[libre-riscv-dev] Michael - New Member whygee at f-cpu.org
[libre-riscv-dev] Some general instruction ideas whygee at f-cpu.org
[libre-riscv-dev] Some general instruction ideas whygee at f-cpu.org
[libre-riscv-dev] Name change from Libre-RISCV to Libre-SOC whygee at f-cpu.org
[libre-riscv-dev] Name change from Libre-RISCV to Libre-SOC whygee at f-cpu.org
[libre-riscv-dev] Wishbone Arbiter whygee at f-cpu.org
[libre-riscv-dev] Wishbone Arbiter whygee at f-cpu.org
[libre-riscv-dev] Wishbone Arbiter whygee at f-cpu.org
[libre-riscv-dev] Michael - New Member mtnolan2640 at gmail.com
[libre-riscv-dev] test mtnolan2640 at gmail.com
[libre-riscv-dev] Michael - New Member mtnolan2640 at gmail.com
[libre-riscv-dev] introduction to Formal Mathematical Proof team haael
[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal haael
[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 151] New: introductory formal verification tutorial using the PriorityPicker bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 151] introductory formal verification tutorial using the PriorityPicker bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 151] introductory formal verification tutorial using the PriorityPicker bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 151] introductory formal verification tutorial using the PriorityPicker bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 151] introductory formal verification tutorial using the PriorityPicker bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 151] introductory formal verification tutorial using the PriorityPicker bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 151] introductory formal verification tutorial using the PriorityPicker bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 151] introductory formal verification tutorial using the PriorityPicker bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 151] introductory formal verification tutorial using the PriorityPicker bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 70] evaluate Bus Architectures bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 70] evaluate Bus Architectures bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 152] New: evaluate if hardware support for vulkan bytecode is viable bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 152] evaluate if hardware support for vulkan bytecode is viable bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 70] evaluate Bus Architectures bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 70] evaluate Bus Architectures bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 153] New: Top-level for NLNet 2019.10 ASIC Cell Libraries Project. bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 153] Top-level for NLNet 2019.10 ASIC Cell Libraries Project. bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 153] Top-level for NLNet 2019.10 ASIC Cell Libraries Project. bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] New: Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 153] Top-level for NLNet 2019.10 ASIC Cell Libraries Project. bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 155] New: a PLL is needed for the SoC bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 156] New: different versions of DependencyMatrix bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 157] New: after dual ISA support is added for usersoace RV64GC add priv space as well bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 17] IOMMU needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 17] IOMMU needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 151] introductory formal verification tutorial using the PriorityPicker bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 158] New: NLNet 2019 Formal Correctness Proofs toplevel bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 158] NLNet 2019 Formal Correctness Proofs toplevel bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 159] New: opcode ideas, suitable for audio/video (and more) bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 159] opcode ideas, suitable for audio/video (and more) bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 160] New: wiki git repo way out of date bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 160] wiki git repo way out of date bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 17] IOMMU needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 17] IOMMU needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 74] preliminary exploratory software emulation of FP SQRT bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 161] New: Create Shader Compiler IR and SPIR-V to IR translator bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 74] preliminary exploratory software emulation of FP SQRT bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 130] FMIN/MAX needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 130] FMIN/MAX needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 74] preliminary exploratory software emulation of FP SQRT bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 130] FMIN/MAX needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 130] FMIN/MAX needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 130] FMIN/MAX needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 130] FMIN/MAX needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 130] FMIN/MAX needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 162] New: Formally Verify the FSGNJ module bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 163] New: Formally Verify the FPMAX module bugzilla-daemon at libre-riscv.org

Last message date: Fri Jan 31 23:36:22 GMT 2020
Archived on: Tue Feb 4 17:51:09 GMT 2020

Messages sorted by: [ thread ] [ subject ] [ date ]
More info on this list...

This archive was generated by Pipermail 0.09 (Mailman edition).