[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=132

--- Comment #40 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i've started on the PartitionedSignal class, and have plumbed in
PartitionedAdder
and confirmed that it works:

https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part/partsig.py
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part/test/test_partsig.py

it's relatively straightforward (mainly thanks to jacob already having
created PartitionedAdder).  am currently doing "eq" which will be an
override of Signal.__eq__.

https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part_cmp/equal.py

this is slightly tricky because the response changes depending on the
partitioning, i.e. represents either a BOOL (single-value) or an *array*
of BOOLs (SIMD comparisons).

this kinda has to be defined otherwise we get into a bit of a mess.

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